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Senior Design Verification Professionals_Eximietas Design
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Formal Verification Engineer
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Senior Engineer – ASIC Verification - Bangalore, Hyderabad, Noida, Chennai, Ahmedabad, Pune
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VLSI Chip Designer
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Design Verification Engineer
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STA Engineer
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Senior Analog Design Engineer
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Functional Safety Engineer
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Physical Design & Implementation Engineer — High-Speed Automotive SerDes SoCs (3–5 Yrs)
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Lead STA Engineer
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Immediate hiring for Analog Layout - HYD Location
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PD EMIR Engineer
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Coherency Design Verification Engineer (CHI / Multicore CPU)
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Senior Physical Design Engineer
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RTL Design Engineer
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Senior Design Verification Engineer
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Senior Memory Layout Engineer
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VLSI CAD Engineer – SoC IP Enablement & Front-End TFM
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DFT Engineer
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Design Verification Lead
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RTL Design Lead
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Design Verification Engineer
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Verification Engineer – Ethernet Protocol
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Manager - Channel Partner Acquisition
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Chief Growth Officer
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Assistant Professor - CSE
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General Manager / Production Head - Refractory
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