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DFT Architect
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Principal Engineer – STA
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SMTS Verification Engineering
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MTS, DIGITAL; DSGN
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Uniserved (Backup Admin Sme )
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Staff Engineer, System Design Engineering
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Engineering System Engineer
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PCIe design Architect
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LeadSoc ( DFT Consultant )
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Principal Engineer – RV (EM/IR)
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Sr Engineer, Design Enablement
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Lead IP Block level Verification Engineer
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Senior Engineer, ASIC Development Engineering (PD, PV Signoff, STA Signoff Flows)
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Senior Engineer, Digital Design Engineering
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VLSI Trainer (Visiting Faculty)
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Lead Application Engineer - GCS ( Physical Design )
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Staff Engineer – DFT Engineering
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Lead Systems Engineer
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Sr Principal Product Engineer
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Lead Support Application Engineer - GCS
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Lead Support Application Engineer - GCS
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Manager - Drives Commissioning & Testing
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Staff / Principal Engineer - NAND FA
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Senior Engineer – Static Timing Analysis (STA)
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Staff Design Verification Engineer
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Senior Manager, VLSI Design Engineering ( IO Design (LVCMOS, HVCMOS, DDR, LVDS)) with 15+ Years of experience
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Senior CAD Engineer
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Sr Principal Design Engineer
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Manager - Drives Commissioning & Testing
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Engineer, HIG HBM Layout
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Layout engineer
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Architect MTS
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Sr Physical Design Engineer
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Technologist, VLSI Design Engineering
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Principal Design Engineer
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Lead Support Application Engineer - GCS
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Principal CAD Engineer
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Senior Engineer II - Design Engineer
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Staff Engineer – Static Timing Analysis (STA)
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Senior Staff Engineer – PV (Physical Verification)
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MTS, HIG-HBM Layout
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Layout Engineer, DPG IP DEV Layout
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Staff Physical Design Engineer
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SR ENGINEER, HIG HBM LAYOUT
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Principal Design Engineer
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FPGA SW Validation Engineer
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End User Engineer II
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