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Lead Silicon Design Engineer (FPGA Silicon Architecture/CAD & EDA Flows)
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Physical Design / PnR Lead
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Full-Stack Developer
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Staff Engineer – DFT Engineering
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Account Technical Executive
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Senior AMS Design Verification Engineer / AMS DV Lead
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CAD Design Engineer
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End User Engineer II
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SOC verification Manager/Lead
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Design engineering Architect
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Sr Principal Design Engineer
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Design Manager
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Principal CAD / AI Methodology Lead, ASIC Infrastructure Development
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Sr Engineer, Design Enablement
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Staff Engineer, Design Enablement
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Integration Support Executive
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Senior Engineer II - Design Engineer
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Layout Engineer, DEG Layout
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STA Lead
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Regional Visicooler Manager - West
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Principal Engineer, VLSI Design Engineering (Verification, NAND, Memory, System Verilog) with 8 to 12 years of experience
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Full Stack Developer
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MTS, HIG-HBM Layout
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Senior Manager, VLSI Design Engineering ( IO Design (LVCMOS, HVCMOS, DDR, LVDS)) with 15+ Years of experience
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Layout Engineer, DPG IP DEV Layout
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Principal Engineer - Physical Design
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Staff Engineer, EM/IR
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Staff Layout Engineer-DPG-LPDDR
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Layout engineer
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Senior Data Engineer
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STA Lead
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Senior Data Engineer
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Senior Network Infra Engineer- (L3)- Change - Pune - Hybrid Contract
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Associate Professor- Computer Architecture
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Physical Design & Implementation Engineer — High-Speed Automotive SerDes SoCs (3–5 Yrs)
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Senior Data Engineer
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Digital Logic Design Engineer
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Functional Safety Engineer
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Digital Design & RTL Engineer — High-Speed Automotive SerDes SoCs (3–10 Yrs)
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Senior Data Engineer
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Assistant Professor - Computer Science Engineering
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Senior AI + Fullstack Engineer
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Senior AI + Fullstack Engineer
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STA Lead
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Functional Safety Engineer
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Design Verification Engineer
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Circuit Design Engineer
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Senior Data Engineer
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