Technical lead
Silicon Patterns • Bengaluru, Karnataka • Posted June 03, 2026
About the Role
Hiring!
DV Design Verification
PCIe Logic Verification (8+ yrs)
End-to-end verification of PCIe controller/subsystem (Gen5/6/7).
Role:
Verify PCIe protocol
Debug RTL/testbench/system issues
Strong System Verilog & UVM
DV Design Verification
PCIe Logic Verification (8+ yrs)
End-to-end verification of PCIe controller/subsystem (Gen5/6/7).
Role:
Verify PCIe protocol
Debug RTL/testbench/system issues
Strong System Verilog & UVM