Senior SoC Verification Engineer - UVM/Automation Expert

TetraMem in Singapore is seeking an experienced Verification Engineer to join their team. The ideal candidate will have a strong background in SoC design verification with responsibilities that include developing test plans, building verification infrastructure, and mentoring team members.

A successful applicant will hold either an MS with 8+ years of experience or a PhD with 3+ years in related fields, alongside expertise in various verification methodologies and programming languages.