Senior FPGA/ASIC Design Engineer - Hybrid, Lead & RTL

A leading semiconductor company in Malaysia seeks an experienced ASIC/FPGA Design Engineer to develop and maintain RTL designs using Verilog/System Verilog. Candidates should have 5+ years in RTL/Logic design, strong analytical and problem-solving skills, and the ability to collaborate effectively with cross-functional teams. Knowledge of guidelines and coding standards is essential, alongside familiarity with tools like Quartus and Vivado. The role offers a hybrid work model, balancing on-site and off-site work.
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