Senior CPU RTL Engineer - RISC-V

Bitdeer, headquartered in Singapore, is looking for an experienced CPU/Processor Design Engineer to develop Verilog RTL for RISC-V based CPU architectures. You will work on ensuring functional coverage and debugging processes while collaborating closely with various teams to deliver high-quality processor IP.

The ideal candidate will have a Master’s or Bachelor’s degree in Electrical Engineering or Computer Engineering, along with relevant R&D experience. The position offers an inclusive environment with attractive welfare benefits and growth opportunities.