Senior Cmos Test Structure Design & Layout Engineer (San Pedro Tlaquepaque)

Responsibilities
Micron Technology, Inc is seeking a Senior Engineer to support development activities involving memory cell test structures.
Qualifications
The adecuado candidate will have at least 5 years of experience and proficiency in EDA tools including Cadence Virtuoso and Calibre. The role requires excellent skills in circuit building, layout, and verification, along with a deep understanding of semiconductor device physics.
Benefits
Benefits include medical, dental, and vision plans, paid family leave, and robust paid time-off programs.
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