Senior ASIC Digital Design Engineer at Synopsys
Synopsys, Inc. • ottawa, on • Posted July 09, 2026
About the Role
Drive innovation at Synopsys as a Senior ASIC Digital Design Engineer. Your expertise in RTL design and high-speed digital interfaces will shape the future of memory technologies.
With 7-10 years of hands-on experience, you’ll develop high-performance RTL designs for High Bandwidth Memory PHY IP. Collaborate with cross-functional teams, and tackle complex technical challenges while ensuring seamless integration and performance optimization. Your communication skills will be vital in mentoring junior engineers and guiding technical efforts within the team.
Key Responsibilities:
• Develop RTL designs for High Bandwidth Memory PHY IP
• Translate architectural requirements into robust RTL implementations
• Collaborate with teams for optimal integration and performance
• Innovate solutions for timing closure and low-power design
• Automate design tasks using scripting languages
Requirements:
• 7-10 years of experienc...
With 7-10 years of hands-on experience, you’ll develop high-performance RTL designs for High Bandwidth Memory PHY IP. Collaborate with cross-functional teams, and tackle complex technical challenges while ensuring seamless integration and performance optimization. Your communication skills will be vital in mentoring junior engineers and guiding technical efforts within the team.
Key Responsibilities:
• Develop RTL designs for High Bandwidth Memory PHY IP
• Translate architectural requirements into robust RTL implementations
• Collaborate with teams for optimal integration and performance
• Innovate solutions for timing closure and low-power design
• Automate design tasks using scripting languages
Requirements:
• 7-10 years of experienc...