Principal IC Packaging Engineer

Piper Companies is seeking a Principal IC Packaging Engineer who will develop and refine Chip-on-Wafer-on-Substrate technology. The Packaging engineer will be onsite 5 days a week in Saratoga, CA.

Requirements for the IC Packaging Engineer include:

-Innovate and enhance CoWoS packaging processes to boost chip performance, power efficiency, and reliability.

-Collaborate with design, test, and manufacturing teams to ensure flawless chip-package integration.

-Lead failure analysis and drive yield improvements across packaging processes.

-Ensure CoWoS packaging meets all thermal, mechanical, and electrical performance standards.

-Support new product introduction (NPI) from initial prototyping to high-volume manufacturing.

-Partner with foundry and OSAT partners (e.g., TSMC, ASE, Amkor, SPIL) on process qualification and production ramp-up.

Qualifications for the IC Packaging Engineer include:

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