Physical Design Engineer

We are seeking expert Physical Design Engineers to lead top-level signoff activities for complex SoCs on advanced nodes (5nm / 3nm / 2nm). The ideal candidate will have multiple full-cycle tapeouts and the technical depth to independently drive signoff-to-tapeout closure. This role requires close collaboration with RTL, Timing, Power Integrity, and Foundry teams to ensure structural integrity, timing convergence, and power reliability for high-performance silicon.

Core Responsibilities

• Drive top-level signoff for high-performance SoC designs.
• Collaborate with RTL, Physical Design, STA, and cross-functional teams.
• Execute, analyze, and debug complex full-chip design challenges.
• Develop and optimize signoff methodologies to improve TAT (Turn-Around Time) and PPA (Power, Performance, Area).
• Identify and mitigate timing, power, reliability, and clocking risks at full-chip level.
• Deliver signoff closure and...