DFT Design Engineer
Cadence Design Systems, Inc. • Austin, TX • Posted June 22, 2026
About the Role
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
US citizenship Required
We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST) and automatic test pattern generation (ATPG) is required for this position. Should follow systematic quality metrics driven ATPG pattern generation. It is highly desirable for candidate to possess hands-on knowledge of synthesis, verification and debugging Verilog testbenches.
Requirements;
+ Prior 2-10 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT)
+ Should possess intimate knowledge of DFT insertion flows
+ Basic scan chain insertion using synthesis or other software tools
+ Experience in compression scan insertion, LBIST and other scan tec...
US citizenship Required
We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST) and automatic test pattern generation (ATPG) is required for this position. Should follow systematic quality metrics driven ATPG pattern generation. It is highly desirable for candidate to possess hands-on knowledge of synthesis, verification and debugging Verilog testbenches.
Requirements;
+ Prior 2-10 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT)
+ Should possess intimate knowledge of DFT insertion flows
+ Basic scan chain insertion using synthesis or other software tools
+ Experience in compression scan insertion, LBIST and other scan tec...