Design Verification Engineer

Kuala Lumpur, Malaysia | Posted on 02/26/2026

• Country Malaysia

Job Description

• Develop testbench components such as test, sequence libraries, bfm and monitor by usingobject oriented programming verification techniques following UVM methodology
  
• Automate validation environment to improve activities such as test writing, regressionrunning or coverage collection
  
• Define detailed test plan from specification by working with architects and design engineers
  
• Write and debug tests in UVM/C++
  
• Incorporate function/code-coverage, assertions, cover-groups etc to achieve 100% verificationcompleteness prior to tapeout
  

Requirements

• Knowledge in C, Python, shell scripting
  
• Great interpersonal and communication skills
  
• Teamplayer, critical thinker and problem solving skills