[ASAP] SoC Physical Implementation Engineer
SUCCESSKOREA • South Korea, South Korea • Posted June 09, 2026
About the Role
채용제목 [ASAP] SoC Physical Implementation Engineer 회사소개 반도체 디자인하우스 업무내용/자격요건 [Job Purpose]
As a Physical Implementation Engineer, you will participate in the synthesis, SDC Clean(GCA), Eauivalence check, DFT(BIST/BIRA/SCAN) Design&verification, UPF low power design and Static Timing Analysis(Timing Closure).
[Principal Accountabilities]
- DFT Implementation
- SCAN insertion / ATPG / Scan Simulation (Test Compiler / TetraMax)
- BIST/BIRA Insertion & Simulation : Tessent MBIST / JTAG / IJTAG
- SDC Creation & Clean
- Spyglass LINT/SDC/DFT Check
- Logic Synthesis : DC/DCT/DCG
- Equivalence Check : Formality/Conformal
- LDRC : Logic Design Rule Check (Spyglass_LDRC)
- STA (Static Timing Analysis)
- Timing Closure : cross-talk/noise/mttv/setup/hold fix (Prime_Time, Physical-aware ECO)
- Low Power Design : UPF Creation & Low power Rule Check(VC_LP)
- Multi-voltage, Multi power domain, Power-gating, Clock-gating.
- Power Analysis :...
As a Physical Implementation Engineer, you will participate in the synthesis, SDC Clean(GCA), Eauivalence check, DFT(BIST/BIRA/SCAN) Design&verification, UPF low power design and Static Timing Analysis(Timing Closure).
[Principal Accountabilities]
- DFT Implementation
- SCAN insertion / ATPG / Scan Simulation (Test Compiler / TetraMax)
- BIST/BIRA Insertion & Simulation : Tessent MBIST / JTAG / IJTAG
- SDC Creation & Clean
- Spyglass LINT/SDC/DFT Check
- Logic Synthesis : DC/DCT/DCG
- Equivalence Check : Formality/Conformal
- LDRC : Logic Design Rule Check (Spyglass_LDRC)
- STA (Static Timing Analysis)
- Timing Closure : cross-talk/noise/mttv/setup/hold fix (Prime_Time, Physical-aware ECO)
- Low Power Design : UPF Creation & Low power Rule Check(VC_LP)
- Multi-voltage, Multi power domain, Power-gating, Clock-gating.
- Power Analysis :...