Analog Design Engineering Manager
Intel • Phoenix, AZ • Posted June 09, 2026
About the Role
**Job Details:**
**Job Description:**
The Hard IP and Test Chip Development team, within Intel's Central Engineering Group, is responsible for delivering industrydefining analog and mixedsignal IP for Intel's Client, Datacenter, AI and Foundry customers. The IO team owns high-speed serial IO and die-to-die interfaces across multiple advanced process nodes. As a senior analog design engineering manager, you will lead technical teams to deliver IP that will shape Intel's future of IO and chiplet interconnect technology.
This engineering manager role will be responsible for the following:
• Technical Leadership: Guiding the design of analog circuits (e.g., ADCs/DACs, Phase Interpolators, voltage regulators) and ensure high-quality silicon through all phases of planning, tech readiness, pre-silicon design, and post-silicon validation. Enabling engineers to focus on high ROI activities by driving efficiency throughout the development cycle, including the adoption of automa...
**Job Description:**
The Hard IP and Test Chip Development team, within Intel's Central Engineering Group, is responsible for delivering industrydefining analog and mixedsignal IP for Intel's Client, Datacenter, AI and Foundry customers. The IO team owns high-speed serial IO and die-to-die interfaces across multiple advanced process nodes. As a senior analog design engineering manager, you will lead technical teams to deliver IP that will shape Intel's future of IO and chiplet interconnect technology.
This engineering manager role will be responsible for the following:
• Technical Leadership: Guiding the design of analog circuits (e.g., ADCs/DACs, Phase Interpolators, voltage regulators) and ensure high-quality silicon through all phases of planning, tech readiness, pre-silicon design, and post-silicon validation. Enabling engineers to focus on high ROI activities by driving efficiency throughout the development cycle, including the adoption of automa...